I. Field of the Disclosure
The present disclosure relates generally to the design and testing of a memory device and more specifically relates to a method and device for testing memory.
II. Description of the Related Art
A memory device, such as a random access memory (RAM), can have multiple arrays including multiple storage elements. An array can have word lines and bit lines that allow for storing binary data in addressable storage elements. Errors such as shorts between bit lines may occur during manufacture or during use of a RAM. A built-in-self-test (BIST) can be used for detecting such errors.
However, in some processor architectures operating in a BIST mode, a read operation and a write operation could result in data collisions, such as when a BIST read operation and a BIST write operation attempt to access the same register.
Accordingly, it would be advantageous to provide an improved method and device for testing a memory.